1. Technical Field
Embodiments presented herein relate generally to computing systems and processing devices, and, more particularly, to a method and apparatus for implementing a promotion of a speculative operation during a tablewalk in a processing device.
2. Description of Related Art
Processor-based devices such as central processing units (CPUs), graphics processing units (GPUs), or accelerated processing units (APUs) that implement virtual memory systems use a page table to store the mapping between the virtual addresses and physical addresses in memory. Conventional processor-based devices may also implement a translation lookaside buffer (TLB) that can cache mappings of virtual addresses to physical addresses. For example, the TLB can cache virtual-to-physical address mappings of recently requested addresses. The TLB is typically implemented as content-addressable memory (CAM) that uses the virtual address as a search key and the search result is a physical address indicated by the stored mapping. If the requested address is present in the TLB, a TLB hit, the search yields a match and the retrieved physical address can be used to access memory. If the requested address is not in the TLB, a TLB miss, the translation proceeds by looking up the page table in a process called a tablewalk. The tablewalk is an expensive process that involves reading the contents of multiple memory locations and using them to compute the physical address. After the physical address is determined by the tablewalk, the virtual address to physical address mapping is entered into the TLB.
Processor-based devices may also perform speculative operations that can be canceled. For example, a speculative operation could be canceled due to a branch mis-prediction or an older exception. Electrical circuits and devices that execute instructions and process data have evolved becoming faster and more complex. With the increased performance and low power demands of modern data processor architectures (e.g., multi-core processors), considerations for performing tablewalks subsequent to cache misses has become more complex, particularly for speculative operations. In some previous solutions, speculative tablewalks are simply prohibited. In other cases, speculative tablewalks are abandoned or canceled if non-cacheable page table entries were encountered or if page table entries required modification(s). These previous solutions, however, suffer from poor performance and inefficient power utilization.
Embodiments presented herein eliminate or alleviate the problems inherent in the state of the art described above.